wanted one on a desk so i wrote a 16-cell systolic array fabric over summer break. no pc no fetch no decode, 16 cells each holding an op and a direction where data goes in the west side and gets mangled by whatever cell it lands on. runs at 4hz cuz at 16mhz theres obviously nothing to look at.

had to route it on a custom 70mm round 4-layer board. fanning everything out of a qfn-48 on 0.5mm pitch was where all the pain was. wrote a parametric schematic generator to avoid drawing 88 symbols by hand, hit 0 drc violations across 770 tracks and 148 vias, and ended up with two open led nets on b.cu because the east side of the package ran out of escape room.

the board powers and configures and talks in simulation, but oss cad suite isnt installed on this machine so build.sh has literally never run and i have zero timing data.

most of the funding goes to a 5-board assembly run from jlc, physical testing gear like a logic analyzer to probe the open lines, and sorting the software toolchain to compile and flash the bitstream.

if it fails, two leds stay dark or the timing numbers come back completely broken. if that happens i'll use a logic analyzer to see what caused it instead of throwing it away, and patch the copper for a second spin.

Still just me on this again haha. i built the fabric, the generators, the board, and the parametric case myself. $0 raised in the past 12 months.

https://github.com/ranveerlabs/morphcpu