My core research question is whether heavy industry can ever safely hand execution control to autonomous AI agents. The prevailing approach relies on software guardrails that can be bypassed or prompt-injected. My hypothesis takes the opposite path: decompose human mandates into strict mathematical primitives, provide only one atomic execution tool per step, enforce that the physical trigger opens exclusively from the outside (the human mandate), and record every transition onto an immutable, tamper-evident ledger. I authored GUARDAID and Guardalpha to prove this architecture, but theoretical papers cannot protect real infrastructure. This grant funds the empirical stress-testing: an independent engineering team in India building the core without my intervention to generate deterministic binary vectors, and an FPGA testbench to physically verify timing closure on commodity gates. If our timing fails or the logic breaks under real hardware constraints, we document and publish the exact defects.

## What are this project's goals? How will you achieve them?

Specifications rot on paper if they never face external code compilers and physical clock cycles. We are funding two empirical tests:

First, proving GUARDAID Core's determinism. We are hiring two senior developers in India who have never seen or discussed this specification before. Their sole job is building an independent implementation in Rust or Go straight from our public repository. Any ambiguity they hit in the 16-step reading loop won't be resolved in private calls; it gets documented as an errata deliverable.

Second, testing Guardalpha-Cert on real gates. We are bringing in an FPGA engineer to map the four pulse-module components—the execution latch, 2-of-3 voter, hardware identity anchor, and signature channel—onto standard commercial boards to measure real Worst-Case Execution Time (WCET).

We aren't building commercial consumer apps, SaaS dashboards, or taping out production ASICs here. Our only deliverable is verifiable, publicly reproducible engineering data.

## How will you know it worked?

We measure progress through concrete public artifacts, not subjective status reports:

Milestone 1 outputs:

- A clean, independent Rust or Go implementation under Apache-2.0.

- All Part IV conformance tests (~90 edge cases) passing inside an automated CI pipeline.

- Production and open archival of missing binary test vectors (raw cryptographic keys, serialized payloads, runtime contexts, expected outputs).

- Verification across all 78 existing test vectors from Annex 1.

- A public divergence log categorizing every issue as either a code defect or an official spec bug.

Milestone 2 outputs:

- Fully synthesizable RTL released under Apache-2.0.

- Bench validation logs recorded directly from physical FPGA dev boards.

- Hard silicon area and gate propagation delay metrics benchmarked against our 3 kGE estimate.

- A public timing closure report. (Proving timing fails to close on commercial FPGAs is equally valuable, as it halts premature silicon fabrication).

## How will this funding be used?

The $200,000 budget breaks into two independent $100,000 phases:

Phase 1 — Independent Implementation & Test Vectors ($100,000):

- External Dev Team (2 senior developers in India, 6 months): $68,000

- Technical Direction, edge-case adjudication & bench connectivity (me): $10,000

- Grant Administration & corporate compliance (VITRIXY executive lead): $10,000

- Automated CI test rigs, vector storage & distribution: $5,000

- Local dev tooling & environment setup: $4,000

- Cross-border contracts, accounting & banking fees: $3,000

Phase 2 — Hardware FPGA Prototype & Timing Closure ($100,000):

- Specialized FPGA Contractor (6 months): $64,000

- Technical Architecture & hardware verification (me): $10,000

- Operations & board procurement (VITRIXY executive lead): $10,000

- Commercial FPGA dev boards, bench toolchains & test equipment: $10,000

- Hardware measurement logs, reporting & vector archival: $4,000

- Vendor compliance & international administrative costs: $2,000

## Who is on your team? What's your track record on similar projects?

Technical Direction & Author:

Fabiana A. Martínez — Mathematician, System Architect, and author of the GUARDAID and Guardalpha specifications. My background is proven through formal, DOI-registered architecture deposits and test suites on Zenodo and ORCID:

- GUARDAID Core: doi:10.5281/zenodo.23224699

- Annex 4 (Technical & Infrastructure): doi:10.5281/zenodo.23681350 · doi:10.5281/zenodo.23681600

- Registry v3: doi:10.5281/zenodo.23681062

- Annex 1 (Agent Conformance): doi:10.5281/zenodo.23300817 · doi:10.5281/zenodo.23307380

- Guardalpha Suite & Cert Specs: doi:10.5281/zenodo.23522811 · doi:10.5281/zenodo.23224789 · doi:10.5281/zenodo.23223386 · doi:10.5281/zenodo.23585266 · doi:10.5281/zenodo.23585293 · doi:10.5281/zenodo.23585317 · doi:10.5281/zenodo.23585347

- ORCID Record: https://orcid.org/0009-0002-3280-5383

Administration & Corporate Vehicle:

Grant distribution, hardware logistics, and vendor contracts run through our Estonian corporate vehicle, VITRIXY OÜ (Tallinn), under standard EU regulatory and banking oversight. Corporate compliance, contractor management, and hardware import logistics are led by VITRIXY's executive lead.

Independent Contractors:

Two external engineers in India (Milestone 1) and an independent FPGA engineer (Milestone 2), none of whom have had any past contact with the specification text.

## What are the most likely causes and outcomes if this project fails?

1. Outside engineers get stuck on ambiguities in the text: That is treated as an expected outcome, not a project failure. Gaps in the 16-step reading procedure will be exposed publicly and incorporated directly into the standard as official errata.

2. The FPGA prototype fails timing closure: If commercial FPGA gates run too slow to verify cryptographic signatures within the physical pulse window, we publish the negative result. That prevents wasting significant capital on custom silicon tape-outs.

3. Funding reaches only $100k: Milestone 1 is completely self-contained. The independent core and vectors will be fully completed and published even if the FPGA phase is not funded.

## How much money have you raised in the last 12 months, and from where?

$0. The entire specification portfolio and testing architecture have been 100% self-funded through private R&D capital. No VC funding, angel investments, or external grants have been taken.