Project summary

An independent, engineering-grounded feasibility audit of proposed hardware-enabled mechanisms (HEMs) for AI compute governance — chip-level features like on-chip metering and power/thermal monitoring — conducted by a physical design engineer with real chip signoff/verification experience, not a policy researcher reasoning about hardware from the outside.

What are this project's goals? How will you achieve them?

Goal: produce a public technical report that rigorously assesses whether 5-8 of the most-cited proposed HEMs (on-chip compute metering, power/thermal/EM-based workload monitoring) are actually feasible at current semiconductor process nodes, closing a gap where existing policy literature rates these mechanisms "feasible" without real engineering scrutiny.

I'll achieve this by: (1) reviewing the existing HEM literature (RAND 2024 survey, 2026 feasibility taxonomy) to identify the specific technical claims underlying each mechanism; (2) for each mechanism, estimating the realistic noise floor from process variation at 7nm-5nm nodes, and how ambient temperature/workload diversity would affect classification accuracy; (3) estimating real implementation cost in design/verification effort based on comparable work I've done professionally; (4) identifying the cheapest realistic adversarial bypass for each mechanism; (5) writing this up as a public report and posting to LessWrong/EA Forum and arXiv for community and expert scrutiny.

How will this funding be used?

~75% ($9,000): my own time, part-time (~10 hrs/week over 3 months), to conduct the technical analysis and write the report

• ~17% ($2,000): simulation or reference tooling, if needed to model power/thermal signatures more rigorously than back-of-envelope estimates

• ~8% ($1,000): contingency buffer

Who is on your team? What's your track record on similar projects?

Team: solo project, [Lokesh].

Background: 5+ years as a Physical Design and Signoff Verification Engineer, including roles at Synopsys (customer-facing support for DDR PHY memory implementations), HCL Technologies (physical implementation/signoff for Intel Xeon subsystem partitions), and Iresh Technologies (full ASIC physical design flow, IR/EM analysis, DRC/LVS signoff). Direct experience with the exact physical-layer analysis (power signoff, process variation, timing closure) this audit requires.

Track record on this specific kind of project: none yet — this would be my first public research output outside of industry engineering work. I'm starting here deliberately: a scoped, well-defined project like this is how I intend to build a credible, citable public track record before pursuing larger AI safety fellowships.

What are the most likely causes and outcomes if this project fails?

Most likely failure mode: the analysis takes longer than the part-time budget allows, given this is outside my day-to-day paid work, and the report ends up incomplete or covering fewer mechanisms than planned.

Secondary risk: the engineering analysis, once done rigorously, might simply confirm the existing literature's feasibility ratings rather than challenge them — which would still be a useful (if less exciting) contribution, since a rigorous confirmation is also valuable, but is a less compelling "outcome" than an original correction.

If the project stalls, the fallback outcome is a shorter write-up covering whichever mechanisms I completed analysis on, published as-is with clear scope limitations noted, rather than a full report withheld until "complete."

How much money have you raised in the last 12 months, and from where?

I don't know your actual fundraising history. If this is genuinely your first funding request, the honest answer is simply: "None — this is my first funding application." If you've received anything else in the past year (even a work bonus tied to a project, a small grant, prior crowdfunding, etc