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Universal bytecode for any AI models – Enabling Inference on Any Hardware
ProposalGrant
Closes March 31st, 2026$0raised
$50,000minimum funding
$100,000funding goal
Offer to donate
32 daysleft to contribute
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Project summary
The AI ecosystem is deeply fragmented: models from PyTorch/TensorFlow are tied to specific libraries, hardware, and environments, making secure and portable deployment extremely difficult. Running AI across hardware - from data centers to edge microcontrollers—demands custom ports, optimizations, and rewrites. This locks out non-programmers, wastes expert time on boilerplate, and stifles innovation, especially on resource-constrained IoT devices with tight memory and power limits.
I'm building NAC (Neural Architecture Code): a universal Instruction Set Architecture (ISA) and compiler that treats AI models as standardized "genomes." It converts any model into a single, self-contained .nac binary file - "machine code" for AI - that runs on any hardware (GPUs to ESP32 microcontrollers), limited only by memory for the largest tensor.
Key benefits: extreme portability (one file, no code needed), verifiable security (declarative format + static analysis eliminates hidden risks), efficiency (optimizations outperform TFLite Micro on edge), decentralization (shareable artifacts + "phylogenetic tree" of AI for research), and foundation for adaptive AI hardware (ASICs/FPGAs).
The project includes three main open-source components:
• NAC — a universal bytecode ISA for safe and decentralized AI inference: https://github.com/FekDN/NAC
• TISA — a tokenizer instruction set architecture (universal tokenizer with 99% Hugging Face parity across BERT/Llama/GPT-2/T5+): https://github.com/FekDN/T-ISA-Tokenizer-Instruction-Set-Architecture
• MEP — a model execution orchestration layer: https://github.com/FekDN/Model-Execution-Pipeline-MEP-ISA
All code, tests, and results are public on GitHub.
What are this project's goals? How will you achieve them?
Finalize a robust NAC standard integrating TISA & MEP.
Validate across hundreds of models (LLM/CV/Audio) and hardware (ARM/RISC-V/ESP32/STM32).
Port compiler + runtime to C++/Rust/Verilog for high-performance, Python-free SDK.
Optimize for edge devices.
Produce documentation, tutorials, and community engagement to drive adoption.
Build incrementally on existing solo prototypes (already executing models on microcontrollers with matching outputs and TISA achieving near-perfect tokenizer parity). Use comprehensive test suites for validation, conduct security/performance audits, rewrite performance-critical parts in lower-level languages, and share progress openly on GitHub to attract contributors.
How will this funding be used?
Seeking $50k–$100k (flexible). Approximate breakdown:
60% ($30k–$60k): Hire 1–2 high-level specialists (bytecode/AI internals/hardware experts) for 3–6 months part-time collaboration - niche skills make this expensive.
20% ($10k–$20k): Testing hardware (Xilinx Artix FPGA boards, ESP32/ARM Cortex/STM32 dev kits).
10% ($5k–$10k): PC upgrade (more RAM/storage for large-model testing).
10%: Tools, cloud compute for benchmarks, conference travel, open-source bounties.
Transparent monthly updates and GitHub milestones.
Who is on your team? What's your track record on similar projects?
Solo developer so far (Dmitry Feklin). Built the entire NAC/TISA/MEP ecosystem without external resources - working prototypes execute models on microcontrollers with identical outputs to originals, TISA matches Hugging Face tokenizers on dozens of models (BERT, Llama, etc.), and full test suites prove high accuracy.
Personal Challenge: As a solo developer, I've generated a flood of interconnected ideas at last time, jumping between them not from lack of focus, but from fear of losing fleeting insights. The project has ballooned into a complex system involving bytecode, low-level model structures, tokenization principles, orchestration, and microcontroller architectures. It's now too large to finish alone - I need a high-level specialists to collaborate, but they're expensive due to the niche expertise required.
Seeking to expand the team with 1–2 specialists via funding.
What are the most likely causes and outcomes if this project fails?
Most likely causes: Insufficient funding → can't hire needed expertise or buy hardware → progress stalls on solo bandwidth and current limited setup.
Technical dead-ends in hardware ports or dynamic features (e.g., control flow).
Low community adoption despite open code.
Outcomes if failure: Project remains a promising but incomplete proof-of-concept on GitHub. No major harm - existing components (TISA parity, NAC inference on MCUs) stay useful as references.
How much money have you raised in the last 12 months, and from where?
$0. This is the first public funding request; all development has been 100% self-funded and solo.