1. What are this project’s goals? How will you achieve them?

**Goal:** Bypass the CMOS "Energy Wall" by replacing energy-wasting multipliers and capacitive switching dissipation with passive photonic wave interference and reversible adiabatic logic, executing exascale AI inference within a 16.32W power envelope (~12.16 aJ/op).

**How we achieve this:**

We have taken TROPOS-1 from theoretical physics to full pre-silicon closure through four unified pillars:

1. **Passive Optical Wave Interference:** Matrix-vector multiplication executed passively via light propagation in an engineered gradient-index (GRIN) medium, consuming zero dynamic switching power.

2. **Multiplier-Free Tropical Arithmetic:** Moving to the (min, +) tropical semiring via Maslov dequantization, replacing silicon-heavy multipliers with log-domain adders (~24× energy reduction).

3. **Reversible Adiabatic Logic:** Utilizing bijective Fredkin gates with 98% modeled energy recovery to fundamentally eliminate Landauer information-erasure dissipation in the datapath.

4. **Sheaf-Based 3D Locality:** Sub-micron vertical hybrid bonding fusing memory directly above compute tiles to eliminate off-chip memory-movement penalties.

**Current Validation & Artifacts:**

- Pre-silicon closure achieved: Synthesizable SystemVerilog RTL (0 testbench errors), 2D Helmholtz FDFD wave-equation simulations, and generated photonic GDSII layout.

- Validated with 0.9999999976 cosine similarity against IEEE FP32 on LLaMA-3 attention kernels.

- Cryptographically anchored to Bitcoin block #961628.

- Technical Memorandum (Zenodo DOI): https://doi.org/10.5281/zenodo.22637552

- Live Verification Console: https://tropos-1.tropos-arch.workers.dev

- Gate-Level Trace Demo: https://youtu.be/kPoNaqUtTb0

2. How will this funding be used?

Total Target Funding: **$50,000** (Non-dilutive). We structure deployment across two sequential, de-risking milestones:

- **Milestone 1 ($25,000 - Tapeout Readiness & Tooling):**

- Securing an initial Multi-Project Wafer (MPW) test-chip slot via imec Europractice silicon-photonics runs.

- 3D full-vector electromagnetic and multiphysics co-simulation tooling to finalize thermal drift tolerances and waveguide phase-error margins.

- **Milestone 2 ($25,000 - Fabrication & Physical Characterization):**

- Silicon fabrication completion and ceramic test packaging (including fiber-array optical coupling).

- High-frequency lab bench testing to validate actual energy dissipation against our 12.16 aJ/op model.

- Covering international PCT patent specification filings (20-claim architecture).

3. Who is on your team? What's your track record on similar projects?

- **Sina Rahimi Kashkooli — Lead Computer Architect & Researcher:** Over the past two years, I developed TROPOS-1 from first-principles physics through synthesizable RTL, numerical wave-equation modeling, and GDSII generation entirely outside traditional institutional labs and without venture backing.

- **Nima Rahimi Kashkooli — Co-founder & Operations Lead:** (nimaalirahimi123@gmail.com), managing legal compliance, cross-border logistics, and our transition into a Belgian corporate entity (BV) in Leuven in synergy with the imec ecosystem.

4. What are the most likely causes and outcomes if this project fails?

- **Primary Technical Failure Mode:** Waveguide fabrication variations and thermal phase drift during the imec MPW run, leading to higher optical insertion loss than modeled.

*Mitigation:* We use passive interference geometries with wide drift tolerances. Furthermore, our executed stress-corner models show that under a combined worst-case 9 dB loss, the system derates gracefully to 1.00 ExaOp/s @ 1.9 GHz rather than suffering catastrophic failure.

- **Secondary Failure Mode:** Sub-micron 3D vertical hybrid bonding yield issues on experimental multi-project wafers.

*Mitigation:* The optical compute core and adiabatic electronic tier are partitioned to be characterized independently on planar test dies before final 3D heterogeneous stacking.

- **Outcome if it fails:** All mathematical proofs, tropical transformer compiler mappings, SystemVerilog RTL, and simulation logs remain permanently archived with open-science provenance on Zenodo for the broader systems research community.

5. How much money have you raised in the last 12 months, and from where?

**$0.** The project has been 100% self-funded and bootstrapped to date. We have reached full pre-silicon closure wi

thout institutional grants or venture capital.